module LFSR #(
    parameter INITVAL = 4'b1011
)(
    input logic clk,       // 时钟信号
    input logic reset,     // 异步复位信号
    output logic out  // 4位输出
);

logic[3:0] lfsr_r;


always_ff @(posedge clk) begin
    if (reset) begin
        lfsr_r <= INITVAL;
    end else begin
        lfsr_r[3] <= lfsr_r[2];
        lfsr_r[2] <= lfsr_r[1] ^ lfsr_r[3];
        lfsr_r[1] <= lfsr_r[0] ^ lfsr_r[3];
        lfsr_r[0] <= lfsr_r[3];
    end
end

assign out = lfsr_r[0];

endmodule
